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Data Sheet
ADV7403
Pin No.
15
Mnemonic
SFL/SYNC_OUT
Type 1
O
Description
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when the decoder is connected to any Analog
Devices, Inc., digital video encoder.
Sliced Sync Output Signal (SYNC_OUT). This pin is only available in CP mode.
16, 82
SCLK1, SCLK2
I
I 2 C Port Serial Clock Input (Maximum Clock Rate of 400 kHz) Pins. SCLK1 is the clock
line for the control port, and SCLK2 is the clock line for the VBI data readback port.
19, 81
SDA1, SDA2
I/O
I 2 C Port Serial Data Input/Output Pins. SDA1 is the data line for the control port, and
SDA2 is the data line for the VBI readback port.
35
DCLK_IN
I
Clock Input Signal. This pin is used in 24-bit digital input mode (for example, processing
24-bit RGB data from a DVI receiver IC) and also in digital CVBS input mode.
36
LLC1
O
Line-Locked Output Clock for Pixel Data. This pin range is 12.825 MHz to 140 MHz for
the ADV7403 KSTZ-140, and 12.825 MHz to 110 MHz for the ADV7403 BSTZ-110.
37
XTAL1
O
Connect this pin to the 28.63636 MHz crystal, or if an external 3.3 V, 28.63636 MHz
clock oscillator source is used to clock the ADV7403 , leave this pin as no connect. In
crystal mode, the crystal must be a fundamental crystal.
38
XTAL
I
Input Pin for 28.63636 MHz crystal. To clock the ADV7403 , this pin can also be
overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source.
46
47, 48
49, 50, 60, 66
51
52
53 to 58, 71 to 76
59
61, 62
63
64
65
67
ELPF
PVDD
AGND
FB
SOG
AIN1 to AIN12
TEST1
CAPY1, CAPY2
AVDD
REFOUT
CML
BIAS
O
P
G
I
I
I
O
I
P
O
O
O
External Loop PLL Filter. Connect the recommend external loop filter to the ELPF pin.
PLL Supply Voltage (1.8 V).
Analog Ground.
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
Sync on Green Input. This pin is used in embedded sync mode.
Analog Video Input Channels.
Leave this pin unconnected.
ADC Capacitor Network.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output.
Common-Mode Level (CML) Pin for theInternal ADCs.
External Bias Setting Pin. Connect the recommended resistor (1.35 k?) between the
BIAS pin and ground.
68, 69
70
77
78
CAPC1, CAPC2
TEST0
SOY
RESET
I
NC
I
I
ADC Capacitor Network.
Leave this pin unconnected, or alternately, tie this pin to AGND.
Sync on Luma Input. This pin is used in embedded sync mode.
System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required
to reset the circuitry of the ADV7403 .
79
DE_IN
I
Data Enable Input Signal. This pin is used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI receiver IC).
80
ALSB
I
This pin selects the I 2 C device address for the control and VBI readback ports of the
ADV7403 . When ALSB is set to Logic 0, it sets the address for a write to the control
port to Address 0x40 and the readback address for the VBI port to Address 0x21.
When ALSB is set to Logic 1, it sets the address for a write to the control port to
Address 0x42 and the readback address for the VBI port to Address 0x23.
85
86
VS_IN
HS_IN/CS_IN
I
I
VS Input Signal. This pin is used in CP mode for 5-wire timing mode.
Can be configured in CP mode to be either a digital HS input signal or a digital CS
input signal used to extract timing in a 5-wire or 4-wire RGB mode.
98
FIELD/DE
O
Field Synchronization Output Signal for All Interlaced Video Modes (FIELD). This is a
multifunction pin. It can also be enabled as a data enable signal (DE) in CP mode to
allow direct connection to a HDMI/DVI transmitter IC.
99
VS
O
Vertical Synchronization Output Signal (SDP and CP Modes).
1
G = ground, P = power, I = input, O = output, I/O = input/output, and NC = no connect.
Rev. B | Page 11 of 20
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